Computer System Architecture Course at MIT
Here is the second open-content MIT computer science course
I am posting, called 'Computer System Architecture'.
This course is a study of the evolution of computer
architecture and the factors influencing the design of hardware and
software elements of computer systems. Topics may include: instruction
set design; processor micro-architecture and pipelining; cache and
virtual memory organizations; protection and sharing; I/O and
interrupts; in-order and out-of-order superscalar architectures; VLIW
machines; vector supercomputers; multithreaded architectures; symmetric
multiprocessors; and parallel computers.
Computer
System Architecture Course at MIT
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Computer
System Architecture Course at MIT
Lecture Notes
The course material is divided into five modules, each covering a set of related topics. This section contains the lecture notes for the course.| Ses | Topics |
|---|---|
Module 1 | |
| L1 | History of Calculation and Computer Architecture (PDF) |
| L2 | Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 (PDF) |
| L3 | Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (PDF) |
| L4 | Microprogramming (PDF) |
| L5 | Simple Instruction Pipelining (PDF) |
| L6 | Pipeline Hazards (PDF) |
Module 2 | |
| L7 | Multilevel Memories - Technology (J) (PDF) |
| L8 | Cache (Memory) Performance Optimization (J) (PDF) |
| L9 | Virtual Memory Basics (J) (PDF) |
| L10 | Virtual Memory: Part Deux (PDF) |
Module 3 | |
| L11 | Complex Pipelining (PDF) |
| L12 | Out of Order Execution and Register Renaming (PDF) |
| L13 | Branch Prediction and Speculative Execution (PDF) |
| L14 | Advanced Superscalar Architectures (J) (PDF) |
| L15 | Microprocessor Evolution: 4004 to Pentium 4 (J) (PDF) |
Module 4 | |
| L16 | Synchronization and Sequential Consistency (PDF) |
| L17 | Cache Coherence (PDF) |
| L18 | Cache Coherence (Implementation) (PDF) |
| L19 | Snoopy Protocols (PDF) |
| L20 | Relaxed Memory Models (PDF) |
Module 5 | |
| L21 | VLIW/EPIC: Statically Scheduled ILP (J) (PDF) |
| L22 | Vector Computers (J) (PDF) |
| L23 | Multithreaded Processors (J) (PDF) |
| L24 | Reliable Architectures (J) (PDF) |
| L25 | Virtual Machines (J) (PDF) |
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